Public defence, Electronics, MSc Omar Numan

Title of the thesis: Design and calibration of current-mode compute-in-memory integrated circuits for neural network processing.

Thesis defender: Omar Numan
Opponent: Dr. Elena-Ioana Vatajelu, TIMA Laboratory, Grenoble, France
Custos: Prof. Kari Halonen, Aalto University School of Electrical Engineering 

Artificial intelligence is now found in many small devices like sensors, wearables, mobile systems, and other edge devices. These devices often process data locally rather than sending it all to cloud servers. But running neural networks on standard digital processors uses a lot of energy, mostly because data has to move back and forth between memory and the processor.

This doctoral thesis explored ways to reduce the energy cost of AI computation by bringing memory and computing closer together in integrated circuits. The research focuses on compute-in-memory, where the main neural network calculations are performed directly inside memory-like circuit arrays. The thesis designs and examines current-mode mixed-signal compute-in-memory circuits, where neural network weights are stored in hardware, input data is applied as electrical signals, and results are produced as current.

This work tackles a key challenge: while analog and mixed-signal circuits can save energy, their accuracy can suffer from circuit flaws, temperature shifts, mismatches, voltage drops, and readout errors. The main result of the thesis is a practical, programmable compute-in-memory platform that brings together circuit design, calibration, and system-level control. It features a CMOS-compatible compute-in-memory core built into a system-on-chip with an embedded RISC-V processor, allowing for programmable operation and self-calibration.

The thesis also introduces circuit techniques for reading and converting analog results with lower overhead, calibration methods to reduce and offset errors, compensation for voltage drops in connections, and methods to improve stability as temperatures change. It also presents a hierarchical Verilog-A modeling and co-simulation framework for testing before fabrication. The results show that building reliable AI hardware needs careful coordination of memory cells, analog readout circuits, digital control, calibration, and verification models. These findings can help future edge-AI hardware for smart sensors, IoT devices, embedded vision systems, wearable electronics, and autonomous low-power systems.

Key words: Compute-in-memory, mixed-signal integrated circuits, vector-matrix multiplication, edge AI inference, embedded calibration, temperature compensation, hierarchical Verilog-A modeling.

Thesis available for public display 7 days prior to the defence at Aalto University's public display page.

Contact:
Omar Numan

+358452305811

omar.numan@aalto.fi  
LinkedIn: www.linkedin.com/in/omarnn95