Public defence in Micro- and Nanoelectronic Circuit Design, M.Sc.(Tech.) Kalle Spoof

Public defence from the Aalto University School of Electrical Engineering, Department of Electronics and Nanoengineering
Doctoral hat floating above a speaker's podium with a microphone

The title of the thesis: Integrated True-Time-Delay Beamforming Receivers

Doctoral student: Kalle Spoof
Opponent: Prof. Antoine Frappé, Junia ISEN, Lille, France
Custos: Prof. Jussi Ryynänen, Aalto University School of Electrical Engineering, Department of Electronics and Nanoengineering

Advances in integrated circuit technology, commonly referred to as microchips, have enabled the sophisticated wireless communication systems we all use today. Yet, in order to respond to the demand for ever increasing data traffic volumes, the performance of these systems needs to improve further to increase the capacity of data transfer. Additionally, the power efficiency of the wireless systems needs to improve to reduce the climate impact of the increased data traffic. One technique for improving both the data transfer speed and power efficiency of wireless systems is beamforming. In beamforming systems, the traditional single antenna of the radio is replaced with an array of antennas, and controlling the signals the individual antennas in the array transmit or receive allows fast electronic control over the operating direction. Directing the transmitted signal only towards the receiving user saves energy compared to a single antenna system radiating in all directions. Controlling the directivity also enables multiple users in separate locations to communicate simultaneously on the same frequency channel, allowing more data transfer capacity over the whole network. 

Large data transfer speeds require wide signal bandwidths. Wideband beamforming receivers require implementing delays for the signals of the different antennas for error-free directivity control. The research work in this thesis focuses on a delay implementation that aims to decrease power and area consumption compared to existing integrated circuit delay solutions. The decreased area consumption lowers the fabrication cost in integrated circuits. The functionality of the proposed delay technique is demonstrated with measurements of two fabricated prototype microchips that were designed as part of the thesis work.

Thesis available for public display 10 days prior to the defence at:

Contact information:

Sähköposti  [email protected]

Doctoral theses in the School of Electrical Engineering:

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